Semiconductor integrated circuit devices with elements, e.g., transistors and resists, on an SOI substrate having a semiconductor layer on an insulation film have various advantages, e.g., reduced parasitic capacitance to realize high-speed switching actions of the order of μs or less, high breakdown voltage of 100 V or more and high reliability resulting from prevented latchup or the like. Patent Document 1 describes an SOI substrate, and also trench type element-isolated structure in detail.
FIG. 2 illustrates a trench type element-isolated structure, wherein 1: silicon-supporting substrate, 2: embedded oxide film, 3: element region, 4: embedded polycrystalline silicon film, 5 and 6: each side oxide film, 7: trench and 8: embedded n+ region. As illustrated, the trench 7 isolates the element regions from each other, and the embedded polycrystalline silicon film 4 is placed between the side oxide films 5.
One of a motor-controlling semiconductor devices proposed (e.g., by Patent Document 2) encloses each element by a dielectric material, e.g., silicon oxide film, to insulate between the elements and between the element and substrate at a high voltage to realize a dielectrically isolated semiconductor device with integrated high breakdown voltage elements, large current outputting circuits, and medium and low breakdown voltage logic circuits.
FIG. 19 illustrates a motor driving system which includes a dielectrically isolated semiconductor device having a one-chip inverter, where the semiconductor device integrated on the same wafer is enclosed by the thick frame. The semiconductor device comprises a driving circuit having an IGBT for driving a motor as a load and upper and lower MOS transistors as the basic components; circuit for generating PWM controlling signals; circuit for distributing the signals to each phase, and so forth. It also comprises, although not shown, a control logic circuit working as an interface with a digital control IC which controls the system as a whole, and various protective circuits.
FIG. 20 is a cross-sectional view illustrating a high breakdown voltage IGBT which is disclosed by Patent Document 2 and can be incorporated in the system shown in FIG. 19. FIG. 20 (a) shows a lightly doped region 610 (?) in which IGBT functional regions are formed, such as an n+ heavily doped emitter region (601), gate electrode (602), p+ heavily doped collector region (603), n doped region (630) which encloses the collector region 603, and 620: p doped region (620) in which a channel is formed. Other regions are silicon-supporting substrate (605), first oxide film (606), second oxide film (705), polycrystalline silicon (704) and n+ heavily doped region (740). The oxide films 606 and 705 dielectrically isolate the n−− lightly doped semiconductor region in which the IGBT is formed. FIG. 20 (b) illustrates a state in which a voltage is applied to between the IGBT collector and emitter to block them from each other.
Patent Document 1: JP-A-5-259266 (FIG. 2 (e) and FIG. 6 (d))
Patent Document 2: JP-A-5-136436